A quiet network streamer, AES endpoint, and DAC with precise system control.
UPnP/DLNA streaming, AES input, FPGA routing, dedicated sample-rate conversion, and high-resolution D/A conversion are combined in one fanless enclosure.
This unit is built so the streamer, AES input, FPGA routing, DAC, and output control behave like one audio component. UPnP/DLNA playback handles the network source, the FPGA logic platform handles deterministic routing, and the Dedicated asynchronous SRC stage conditions AES input for final D/A conversion.
The Sharada Audio Control Interface brings the playback controls into one local console: streaming or AES input selection, UPnP/DLNA endpoint refresh, digital output gain, analog output gain, AES input gain, clock source, and SRC mode. The interface keeps operation focused on listening decisions rather than system administration.
| Feature | Details |
|---|---|
| Fanless by design | No fan noise in the listening room, and no fan vibration inside the chassis. |
| UPnP/DLNA streaming | The unit is configured as a network playback endpoint for UPnP/DLNA libraries and control points. |
| Sharada Audio Control Interface | Source mode, gain, clocking, SRC behavior, service refresh, and playback status are controlled in one local interface. |
| Industrial-grade foundation | The fanless platform is selected for long-term stability in a dedicated audio build. |
| FPGA logic platform | The FPGA platform provides dedicated programmable logic, clock management, block RAM, and DSP resources for precise audio routing before conversion. |
| Dedicated asynchronous SRC stage | The 32-bit asynchronous SRC is used as a digital conditioning stage for AES input and sample-rate handoff. |
| AES3 output | Balanced digital output is included for DACs, reclockers, and AES-first systems. |
| High-resolution DAC | 24-bit / 192 kHz D/A conversion is built into the same controlled endpoint. |
| Clock friendly | Internal, AES, and word-clock behavior are part of the digital-system integration. |
The AES FPGA Streamer & DAC has studio-grade output capability, then adds analog output gain, digital gain, and AES input gain so that strength can be matched to real hi-fi systems. The product keeps professional-source drive and headroom without forcing every preamp or amplifier to accept full professional line level.
| Spec | Value | System relevance |
|---|---|---|
| Network playback | UPnP/DLNA streaming endpoint | Network playback is configured without requiring a general-purpose computer in the listening chain. |
| Control interface | Sharada Audio Control Interface | Puts source selection, gain, clocking, SRC mode, service refresh, and status monitoring into one listener-facing console. |
| Input modes | Streaming or AES IN | The same unit operates as a network streamer-DAC or as an AES-fed DAC endpoint. |
| Streaming controls | Streaming endpoint selection, endpoint refresh, currently playing, active process, and system health status | Helps the listener confirm that the desired network path is active before critical listening. |
| Gain controls | Digital output gain, AES input-to-output gain, and analog output gain | Level matching remains available across streaming and AES input modes. |
| AES clock control | On-board clock or AES source clock | The clocking model supports bit-perfect AES-clocked playback or internal-clock compatibility. |
| AES SRC mode | Enabled for compatibility or disabled for bit-perfect AES pass-through | The control interface exposes both compatibility-first and bit-perfect AES behavior. |
| Spec | Value | System relevance |
|---|---|---|
| FPGA | FPGA logic platform | Dedicated programmable logic handles audio routing and digital housekeeping. |
| FPGA logic capacity | 33,280 logic cells, 5,200 slices, 400 Kb max distributed RAM | The FPGA provides room for deterministic routing, control logic, buffering, and future digital refinements. |
| FPGA block memory | 50 x 36 Kb block RAMs, 1,800 Kb total | The FPGA memory resources support synchronous buffering and FIFO-style digital-audio handling. |
| FPGA DSP resources | 90 DSP48E1 slices with 25 x 18 multiplier and 48-bit accumulator | Hardware DSP resources are available for precise digital-audio operations. |
| FPGA clock management | 5 clock management tiles; each includes MMCM and PLL resources | Clock synthesis, distribution, and filtering happen inside a controlled FPGA fabric. |
| FPGA package I/O | The FPGA package class provides ample high-range I/O for the routing design | The FPGA I/O supports the audio, control, and clock signals used in the build. |
| Digital output | Stereo AES3 | The product includes a balanced professional digital handoff for AES-first systems. |
| Routing engine | Zero-latency FPGA-based routing and mixing | FPGA routing stays deterministic without relying on general-purpose software timing. |
| Sample rates | 32 kHz to 192 kHz | Covers common PCM music libraries from standard resolution through high-resolution playback. |
| Audio format | PCM up to 24-bit / 192 kHz playback | Defines the supported high-resolution digital audio format for the product. |
| Spec | Value | System relevance |
|---|---|---|
| SRC device | Dedicated asynchronous SRC stage | Identifies the asynchronous sample-rate conversion stage used in the digital audio path. |
| SRC architecture | 32-bit stereo asynchronous sample-rate converter | Independent input and output clocks isolate upstream timing behavior inside the digital path. |
| Supported SRC resolution | 16-, 20-, 24-, or 32-bit data I/O with 32-bit internal processing | Preserves high-resolution PCM data while giving the digital stage processing headroom. |
| Supported sample rates | Up to 211 kHz device capability | Covers common 44.1, 48, 88.2, 96, 176.4, and 192 kHz PCM libraries with margin. |
| Sample-rate ratios | Upsampling up to 1:8; downsampling up to 7.5:1 | The digital path can normalize or translate between different source and output rate domains. |
| SRC dynamic range | 175 dB A-weighted at 44.1 kHz to 192 kHz; up to 180 dB A-weighted in 44.1/48 kHz conversion cases | Shows the SRC stage is specified well beyond the noise floor of normal downstream analog playback. |
| SRC THD+N | -130 dB at 44.1 kHz to 192 kHz; selected conversion cases specified down to -171 dB | The selected SRC keeps rate conversion below the audible character of the digital path. |
| Jitter attenuation | The asynchronous SRC documentation specifies clock-jitter attenuation behavior | Helps prevent upstream clock instability from directly defining the downstream digital handoff. |
| Digital filter | Linear-phase FIR filter, 0.007 dB max passband ripple, 125 dB stopband attenuation | Maintains frequency-domain accuracy while suppressing unwanted conversion images. |
| SRC package | Asynchronous SRC stage, audio-grade operating range | Publishes the exact SRC ordering option used for this build. |
| Spec | Value | System relevance |
|---|---|---|
| Conversion | 24-bit / 192 kHz D/A | Converts high-resolution PCM into analog output without adding an external DAC box. |
| Analog output | 2 balanced line-level channels | The analog output is built for a noise-resistant balanced connection. |
| Maximum output level | +24 dBu | Strong line-level headroom is preserved for systems that expect professional output levels. |
| Output impedance | <100 ohms | Helps drive downstream line inputs cleanly over typical interconnect lengths. |
| Spec | Value | System relevance |
|---|---|---|
| Sync inputs | AES11 and word-clock input | The unit can lock into external clocking in master-clock systems. |
| Sync output | Word-clock output | The product can participate in a wider synchronized digital chain. |
| Output SNR | >115 dBA A-weighted | Indicates low analog noise relative to the output signal. |
| Output THD+N | <-101 dB at 1 kHz | Measures distortion plus noise at a standard test frequency. |
| Output crosstalk | -130 dB at 1 kHz | Shows strong left/right channel separation at the analog output. |
| Spec | Value | System relevance |
|---|---|---|
| Cooling | Fanless passive-cooling design | Removes fan noise and fan vibration from the listening room. |
| Platform | Industrial-grade fanless platform | Favors long-term stability over consumer-computer convenience features. |
| Use it for | Dedicated streamer-DAC endpoint | Combines playback endpoint, digital routing, conversion, and output control in one audio component. |
| Configuration | Built to order | The final build is matched to software, enclosure, power, and output needs. |
| Role | A one-box network streamer, AES input processor, and DAC for systems that want fewer digital boxes before the preamp or amplifier. |
|---|---|
| Source matching | UPnP/DLNA network playback and AES IN are both available for systems with high-quality digital transports. |
| Output matching | Built-in analog gain matches the DAC output to traditional hi-fi preamps without giving up studio-grade headroom. |
| Digital path choice | SRC can stay enabled for compatibility and jitter attenuation, or be disabled when the AES source and clocking support a bit-perfect path. |
| Control experience | The Sharada Audio Control Interface keeps source mode, gain, clocking, endpoint refresh, and playback status in one local console. |
| Works with | Digital source and D/A endpoint for preamp, attenuator, integrated amplifier, or power-amplifier systems. |
Linear supply design and separated filtering keep compute, FPGA routing, SRC handling, clocking, DAC conversion, and analog output behavior from sharing one noisy electrical environment.
